A data packet is a variable size unit of communication in a network. A router is a switching device that receives packets containing data or control information on one port, and based on destination or other information contained within the packet, routes the packet out another port to the destination (or intermediary destination).
Conventional routers perform this switching function by evaluating header information contained within a first data block in the packet in order to determine the proper output port for a particular packet.
Referring now to FIG. 1a, one type of conventional router includes a plurality of input ports 2 each including an input buffer (memory) 4, a switching device 6 and a plurality of output ports 8. Data packets received at an input port 2 are stored at least temporarily in input buffer 4 while destination information associated with each packet is decoded to determine the appropriate switching through the switching device 6.
Another type of conventional router is referred to as a “non-blocking” router. Referring now to FIG. 1b, a conventional “non-blocking” router includes a plurality of input ports 2 each including an input buffer (memory) 4, a switching device 6 and a plurality of output ports 8 each having an output buffer (memory) 9. In order to avoid blocking conditions, each output port 8 is configured to include an output buffer 9. Each output port can simultaneously be outputting packets as well as receiving new packets for output at a later time. Typically the output buffer 9 is sized to be sufficiently large, such that no data packets are dropped.
Conventional routers, including the routers of FIGS. 1a and 1b, include buffers that are sized to support a particular bandwidth (B). If the input bandwidth is too high, the router will drop data. The amount of input bandwidth is dependent on a number of factors including: the line input rate, the speed of the look-up process, and the blocking characteristics for the switching device. Input bandwidth also relates to the processing power of the packet processor, where the processing power is related to: (1) the delay bandwidth memory, (i.e., more memory is required for bigger and faster systems); and (2) the packet lookup power, (i.e., the ability to determine where to route packets).
A key problem in designing routers is to make them scale to large aggregate bandwidth. Building larger monolithic systems is made difficult by hard technology limits on the integrated circuits in these systems. In addition, long development times for the redesign of a whole system prohibit internet service providers from keeping up with the growth of bandwidth demand. To process a larger amount of bandwidth in a single system (i.e., a bandwidth of an amount N*B where N is a positive integer), the size and to configuration of a conventional router typically has to be modified or redesigned. The process of modifying a router to increase bandwidth capability entails tedious design processes involving risk that the new design will not perform as intended—(or at all), outlay of resources—(both monetary and human), as well as time delays.